The present invention relates to demodulation and, more particularly to a digital FM signal demodulator which detects and corrects errors.
Frequency modulation (FM) has been widely used, for example, in an optical disc device or in a magneto-optic disc device FM has been used to record address information in slightly wobbled tracks of the record medium, known as a minidisc. The wobbled tracks allow the recording apparatus to provide position information of the optical head on the disc without the use of any position detector. Apparatus for recording wobbled tracks (spiral groove) on a record medium is described in U.S. Pat. No. 4,942,565, the disclosure of which is incorporated herein by reference.
One advantageous technique used to record FM digital signals is to invert the polarity, or signal level, at the boundary of data bits as shown in FIG. 9A. As also seen from FIGS. 9A and 9B, a "1" is represented by an inversion at the center of the data bit whereas a "0" is represented by no inversion.
FIG. 10 is a circuit diagram illustrating one embodiment of a demodulator that can be used to demodulate digital FM signals. The demodulator is provided with a D-type (delay) flip-flop 101 for receiving the digital FM signal SA and a clock signal CK as inputs, an exclusive OR (XOR) gate 102 for receiving digital FM signal SA and the Q output (SB) of the D-type flip-flop 101 as inputs, and another D-type flip-flop 103 for receiving output SC of the XOR gate 102 and a sampling clock SD as inputs.
Demodulation processing of the demodulator of FIG. 10 is described herein in conjunction with for example, the input data stream "01100", shown in FIG. 11A. When the input data pattern "01100" of digital FM signal SA (FIG. 11B) is supplied to the data input line D of the D-type flip-flop 101, the D-type flip-flop 101 delays the input data SA by one time period of the clock pulse CK and outputs the data SB (FIG. 11C) to the XOR gate 102.
The XOR gate 102 performs an exclusive OR boolean operation on the input data SA and the Q output data SB of the D-type flip-flop 101. The level of the output SC (FIG. 11D) of the XOR gate 102 is "1" when the data bits of SA and SB are different. The exclusive OR operation is defined as EQU SC=SA.sym.SB Eq. (1)
When the output data SC from the XOR gate 102 is supplied to the data input line D of the D-type flip-flop 103, the D-type flip-flop 103 outputs demodulated data SE (FIG. 11F) in synchronism with the leading edge of each positive clock pulse of the sampling clock SD (FIG. 11E), thereby providing the demodulated data stream "01100". The sampling clock SD is synchronized with the clock signal CK, but is delayed by 1/2 time period of the clock pulse CK.
Although digital FM signals are consistently inverted at the bit cell boundary, the actual point of inversion may shift (fluctuate) during signal transmission due to jitter and disturbances. In such case, the demodulator of FIG. 10 generates erroneous demodulated data because the demodulation is based primarily on the frequency (or pulse width) difference of the data bits "1" and "0".
The erroneous generation of demodulated data using the demodulator of FIG. 10 is described in conjunction with FIGS. 12A-12G, where jitter or other disturbances cause the boundary of the data bits "10" of the input data (FIG. 12A) to be effectively shifted in the direction of the arrow (to the right) in the FM signals SA (FIG. 12B). When the shifted input data stream "01100" of digital FM signal SA is supplied to the data input line D of the D-type flip-flop 101, the D-type flip-flop 101 delays the shifted input data SA by one time period of the clock pulse CK and outputs data SB (FIG. 12C) to the XOR gate 102.
The XOR gate 102 performs an exclusive OR boolean operation on the shifted input data SA and the output data SB of the D-type flip-flop 101.
When the output data SC (FIG. 12D) from the XOR gate 102 is supplied to the data input line D of the D-type flip-flop 103, the D-type flip-flop 103 outputs demodulated data SE (FIG. 12F) in synchronism with the leading edge of each positive clock pulse of the sampling clock SD (FIG. 12E), resulting in erroneous demodulated data pattern "01110" (FIG. 12G) which is different from the input data SA (FIG. 12A). The broken lines in FIGS. 12B-12F represent the correct signal levels.